There are many applications in the field of circuit electronics for charge injection circuits, i.e., for circuits which are capable of injecting/extracting a given amount of electric charge into/from a node in an electric network. Among these is, for instance, the Manhattan distance computation array described in A. Kramer et al., "Flash-Based Programmable Nonlinear Capacitor for Switched-Capacitor Implementation of Neural Networks", IEDM Tech. Dig., pages 17.6.1-4, December 1994.
FIG. 2 of that article shows a charge injection circuit based on the use of a floating gate MOS transistor connected as a capacitor, wherein the injected/extracted charge is dependent on the threshold voltage of the transistor and the width of the voltage step supplied to its control terminal.
FIG. 3 of that article shows an absolute value function computing circuit which is similar to the circuit in FIG. 2. This comprises two floating gate MOS transistors having source and drain terminals which are connected together and to the inverting input of an operational amplifier, and two generators of step-like voltage signals having outputs respectively connected to the control terminals of the two MOS transistors. Accordingly, each MOS transistor operates as an independent charge injector.
As shown in the article, the step width and threshold voltage of the transistors are such that an input-output characteristic is produced in the form of an absolute value function; in particular, the two electric characteristics of the two MOS transistors serve to respectively implement the two branches of the absolute value function, with both steps having a zero initial value.
The article also brings out a limitation of that circuit, namely the fact that floating gate MOS transistors of the standard type have a very high parasitic overlap capacitance which dominates over the channel capacitance. This is a cause of considerable error in the charge injection. One way of partially solving this problem, as suggested in the article, is to use a MOS transistor of a particular type, that is a MOS transistor having its floating gate extended outside the channel area (included between the source and the drain areas) in the vertical direction relative to the channel length, but substantially non-overlapping the source and drain areas. Such a MOS transistor is also known, defined as a non-volatile memory cell, from European Patent Application EP 0 661 756 A1. In this way, the channel capacitance is increased with respect to the parasitic capacitance, but not to a sufficient extent to make it negligible.